Its pipelining appendix and memory chapters define the hazard, speculation and cache vocabulary the list assumes.

Maps C++ onto pipeline mechanisms and shows why a loop-carried dependency chain, not instruction count, paces a loop.

Its opening chapters show how a shipping x86 core implements the textbook pipeline, each rule tied to a mechanism.

Measures the step in cost per access at each cache boundary and the gap a prefetcher hides.

Explains why a second core makes loads and stores reorder and what a barrier drains.

Puts the method before the tools: what to measure, in what order, and how benchmarks mislead.

Places a loop from a byte count and a datasheet bandwidth alone, before any counter is read.

Defines the split of pipeline slots into front end, bad speculation, back end and retiring, the tree profilers report.

Walks from a noisy timing to counters to a named bottleneck, applying roofline and top-down to whole programs.

Shows how to read emitted assembly against its source, so each mechanism is checked in a listing, not assumed.

The origin of the decoupled front end, where the predictor runs ahead of fetch and drives instruction prefetch.

Introduces the decoded micro-op cache and its power case, the structure both x86 vendors later built.

Where AMD states when the op cache feeds micro-ops, and the fusion and alignment rules for hot loops.

Measures rather than quotes each x86 core's misprediction penalty, micro-op cache and loop buffer behaviour.

States what a microcode fix evicts from the decoded cache and which counters show the fall back to legacy decode.

The origin of tag-based renaming and reservation stations, from which every out-of-order issue queue descends.

Shows which chains renaming cannot break, from partial registers to flags, and the zero-cost idioms that do.

Sets the user-space method that measures the window and register files, and which idioms take no physical register.

Defines the dependence graph of an out-of-order core and the critical path through it that sets run time.

Measures latency, reciprocal throughput and port assignment per instruction, the weights a dependence graph needs.

States every stage of one Arm core from fetch to issue, then per-instruction latency, throughput and pipe assignment.

Predicts a real decoder loop's cycle count from its carried chain and issue slots, then measures the prediction.

Predicts a decoder's refill chain from Arm core latencies, fits extra work under it, and measures the gain.

The origin of memory dependence prediction, which lets a load pass older stores and flushes on a wrong guess.

Measures which store and load size and offset pairs forward or stall, and which cores predict memory dependences.

Defines memory-level parallelism as the misses one window overlaps, and shows which core limits cap it.

Introduces the reorder buffer and defines a precise exception as in-order commit of out-of-order results.

Measures that an interrupt lands on the oldest unretired instruction, which decides what a sampling profiler blames.

Shows rename, the active list and precise branch recovery fitted together in one shipped out-of-order core.

Separates perfect from realistic prediction, renaming and aliasing, and shows how little ILP survives the real ones.

Puts circuit delay on wakeup, select and bypass, capping issue width and window size before ILP runs out.

The origin of SMT, where another thread fills one thread's idle issue slots at a cost to both.

Turns window size, issue width and miss events into cycles lost, making an ILP limit a cycle count.

Defines the tagged geometric-history predictor shipped designs converge on, and the limit of what it can learn.

Carries the tagged geometric scheme to indirect jumps and calls, where interpreters and virtual dispatch stall.

Defines the penalty as pipeline refill plus window drain, so it exceeds pipeline depth and is not constant.

Establishes that predictor state is shared and trainable across contexts, the root of every mitigation and its cost.

Defines the indirect-branch and store-bypass controls (IBRS, STIBP, IBPB, SSBD) and states which carry a large cost.

Where AMD states when the op cache feeds micro-ops, and the fusion and alignment rules for hot loops.

Measures rather than quotes each x86 core's misprediction penalty, micro-op cache and loop buffer behaviour.

Measures latency, reciprocal throughput and port assignment per instruction, the weights a dependence graph needs.

Where each latency, throughput and port entry links to its microbenchmark, so any value can be re-run.

Measured per-instruction tables for an Apple AArch64 core, each entry linked to the counter experiment behind it.

Sets the method for finding which hard bound binds a loop, testing its cycles against each in turn.

Models the predecoder, decoders, micro-op cache and loop buffer closely enough to predict front-end bound loops.

Measures what the vendor leaves untimed in an AVX-512 licence change, a throttled phase then a frequency step.

Finds an undocumented optimisation by its counter signature and bandwidth, and sets the method for what manuals omit.

Measures the step in cost per access at each cache boundary and the gap a prefetcher hides.

The origin of the strided-loop method that recovers cache and TLB size, line size, associativity and miss cost.

Names inclusion victims as the cost of an inclusive last-level cache, the case for non-inclusive and victim designs.

The origin of set duelling and bimodal insertion, the adaptive replacement that survives a streaming pass.

Origin of the lockup-free cache, whose miss-status registers keep misses in flight, so a stream beats a chase.

Fixes the paging walk, the page-walk caches, the TLB invalidation rules and what each memory type permits.

Defines the page-walk cache design space and shows why cached partial translations let a walk skip page-table levels.

The origin of the stream buffer that every vendor stream prefetcher descends from, and of the victim cache.

Its opening chapters show how a shipping x86 core implements the textbook pipeline, each rule tied to a mechanism.

Names an Arm server core's load-side and store-side prefetchers, its TLB levels and the bits that disable them.

Explains why a second core makes loads and stores reorder and what a barrier drains.

The store-buffer model of Intel and AMD ordering, tested on hardware, fixing which reorderings a fence pays for.

The formal model Arm adopted into its architecture, and the record of why the non-multicopy-atomic option was dropped.

Measures line-transfer cost between cores by coherence state and distance, the figure behind every contention rule.

The implementers' account of perf c2c, whose worked example reads contended lines, offsets and callers off the report.

Introduces and measures structure splitting and field reordering on real programs, the origin of hot-cold layout rules.

Argues from cache-line utilisation arithmetic that layout must follow the access pattern, the case behind structure of…

Prints a struct's holes, padding and cache-line boundaries from DWARF, so a layout is seen rather than guessed.

Sorts software prefetch into the cases where it helps and hurts, and shows how it mistrains hardware prefetchers.

The kernel's statement of THP: the enabled and defrag knobs, khugepaged, and the counters showing what was obtained.

Measures the fault latency, memory bloat and unfairness that eager THP promotion causes, and shows what removes them.

Sets the checklist that finds the saturated resource before any profiler is opened.

Walks from a noisy timing to counters to a named bottleneck, applying roofline and top-down to whole programs.

The reference for time a CPU sampler cannot see, off-CPU, scheduler and I/O waits, traced at bounded cost.

Makes a tracing hypothesis a one-line experiment over kprobes, uprobes, tracepoints and PMU events.

The design continuous profilers descend from, always-on sampling across a fleet, cheap enough to leave running.

Defines the counting and sampling modes every Linux profiler uses, and the sample record fields, branch stack included.

Defines skid, why a sample lands after the culprit, and how tagging one op through the pipeline removes it.

Defines the architectural counters, what a PEBS sample captures, and why rdtsc counts time, not cycles, under DVFS.

Defines the event encodings and IBS registers for one Zen core, the tables perf's AMD events are derived from.

Defines Arm SPE as perf drives it, one sampled op in flight, the filters, and what a record holds.

The maintainers' walk from perf stat to perf record to perf annotate, with the sample fields each flag sets.

Home of the user guide and cookbook, where each hardware analysis is defined by the events behind it.

The vendor's reference for IBS-driven profiling on Zen, with metric presets defined per core generation.

Records the design decisions, width as sample share and alphabetical rather than time order, behind its reading rules.

Proves a hot function need not be worth optimising, by measuring what speeding up a line does to end-to-end time.

The origin of measurement bias as a term, link order and environment size alone flipping a compiler flag comparison.

Traces run-to-run variation in x86 retired-instruction counts to one extra count per interrupt and per fault.

Defines what each clock counts, NTP-slewed or raw monotonic time, or CPU time, and the resolution call.

The compiler project's recipe for a quiet Linux host, governor, boost, SMT siblings, ASLR, a cpuset and tmpfs.

Documents the barriers that keep the optimiser from deleting the work under test, and repetition statistics.

Places a loop from a byte count and a datasheet bandwidth alone, before any counter is read.

States the counter set and method that put a measured point on the plot in place of a hand-counted intensity.

Measures the roofs with likwid-bench and the point from likwid-perfctr groups on Intel, AMD and Arm server cores.

Adds a roof per cache level against traffic at the core, so a kernel that hits in cache is not plotted as DRAM bound.

Times each level's transfer with overlap rules, predicting a core's rate and the core count where bandwidth saturates.

Defines the split of pipeline slots into front end, bad speculation, back end and retiring, the tree profilers report.

The official home of every TMA formula, event, threshold and level per microarchitecture, from which toplev derives.

Runs the TMA tree on Linux from the spreadsheet and states why multiplexed levels mislead on short or varied workloads.

States the AMD top-down formulas in events for both levels, the metric groups perf stat runs on Zen with no vendor tool.

Defines Arm's top-down as staged stall accounting, first locating the bottleneck and then measuring its resource.

States the serial-fraction bound on speedup, the argument every later scaling law is written against.

Defines scaled speedup, the bound that holds when the problem grows with the processor count instead of staying fixed.

Extends the bound to chips of unequal cores under a fixed area budget, the arithmetic behind big and little cores.

The origin of the coherency term that makes throughput fall, not merely flatten, as processors are added.

Derives the universal scalability law and states the procedure that fits its coefficients to measured throughput.

Proves occupancy equals arrival rate times time in system with no assumption on arrivals or service.

Origin of the bound-and-bottleneck analysis roofline names as its ancestor, and of the asymptotic bounds on throughput.

Proves why open and closed systems answer a load question differently, and when scheduling, not capacity, sets latency.

Origin of the A/S/c notation, and of the embedded chain that solves a queue with non-memoryless arrivals or service.

Derives the wait near saturation from utilisation and arrival and service variance, the formula behind the latency knee.

Its opening chapters show how a shipping x86 core implements the textbook pipeline, each rule tied to a mechanism.

Measures one kernel in both layouts and traces the gain to the gathers the array-of-structures form forces.

Defines interchange, skewing, reversal and tiling as one family and proves when each keeps a loop nest legal.

Traces the drops in a blocked loop's speed curve to self-interference misses, and shows when copying a tile pays.

Where LLVM lists what its loop and SLP vectorisers accept: interleaving, reductions, if-conversion and runtime checks.

Maps each intrinsic to its instruction and CPUID flag, with the vendor's latency and throughput per microarchitecture.

Defines the architectural counters, what a PEBS sample captures, and why rdtsc counts time, not cycles, under DVFS.

Where Arm explains vector-length-agnostic loops and predication, the model that removes remainder loops entirely.

The specification the NEON and SVE intrinsics come from, so it settles what a compiler must accept and what is a bug.

The normative definition of NEON, SVE and SVE2 instructions and of the scalable vector and predicate register model.

Defines sizeless vector types with run-time dispatch, so one source serves SVE and every fixed-width ISA.

Fixes a batch type per ISA and width, the compile-time vector length model, and still reaches NEON and SVE.

Where shuffle-based lookup replacing a byte loop is worked through step by step, with the measurement method spelt out.

Shows branch-free structural indexing with carry-less multiply and shuffles, measured against conventional parsers.

Where that technique ships, with a kernel per ISA and the harness that keeps its published comparisons reproducible.

Decomposes regexes into string and automaton pieces so both run on SIMD, the design inside the matcher Snort embeds.

Counter evidence that current predictors absorb interpreter dispatch, so a branch removal must be measured, not assumed.

Derives the branch-free integer tricks, division by a constant among them, with proofs rather than as a catalogue.

A worked branchless merge with code whose gain vanishes when the compiler emits no conditional move.

Measures branch-free search over sorted, Eytzinger and B-tree layouts, the winner changing with size and prefetch.

Shows a carry-save adder tree in vector registers beating the dedicated instruction, timed as the minimum of many runs.

Shows how a source change alters the emitted instructions across compilers, versions and flags, with nothing installed.

Explains how the signed-overflow and aliasing rules let a trip count be known and a store loop become memset.

Reads the binary that shipped, with source lines and symbolised branch targets, rather than a recompiled snippet.

Predicts loop throughput and port pressure from the scheduling model, and states it models neither front end nor caches.

Measures instruction latency and throughput with counters, so the model llvm-mca predicts from is checked, not trusted.

Lists what each -O level turns on, the inlining limits, and that -Ofast admits transforms invalid for conforming code.

Shows with real codegen that an abstraction is free only when inlining and the ABI allow it, and the cost when either…

Fixes the rule that a non-trivial class goes by reference to a caller-made temporary, the cost a wrapped pointer pays.

States what PLT calls and interposition cost, and the visibility controls a library needs to inline its own exports.

Defines whole-program LTO against partitioned WHOPR, and the LGEN, WPA and LTRANS stages that run -flto in parallel.

Defines the thin link, summaries analysed whole-program then parallel backends, and the cache for incremental rebuilds.

Defines -march against -mtune, the psABI levels, and -mprefer-vector-width, the switch for full-width AVX-512 code.

Defines target_clones, one function per ISA behind a resolver the dynamic linker runs, so a generic build ships AVX-512.

Lists what -ffast-math implies, of which -fassociative-math alone frees a float reduction, and -ffp-contract for FMA.

Where LLVM lists what its loop and SLP vectorisers accept: interleaving, reductions, if-conversion and runtime checks.

Lists what -ffast-math implies, of which -fassociative-math alone frees a float reduction, and -ffp-contract for FMA.

Defines the address-to-source mapping with discriminators that lets a stale production profile still drive FDO.

States why a profile applied to the final binary beats one mapped to source, and the layout passes accuracy enables.

States what full effect needs, relocations kept at link time and a branch-stack sample profile, neither on by default.

States the design, not a result: basic-block sections and a relink, no binary rewrite, so layout needs no disassembly.

Defines the data-race-free contract, sequential consistency for race-free programs and no meaning for a race.

The normative wording for every memory order, fence and read-modify-write, the text a compiler is checked against.

The table that turns each memory order into x86 and Arm instructions, so what an order costs is read off the page.

States what the kernel assumes any CPU may reorder and what each barrier and access primitive guarantees.

Where herd7, litmus7 and klitmus7 live, the tools that run a litmus test against the x86, Arm and kernel models.

Derives counting, partitioning, locking and deferral with code that runs, the textbook the section assumes.

The origin of the queue lock, each waiter spinning on its own line, measured against ticket and test-and-set locks.

Derives a correct user-space mutex from futex and shows the lost wakeups and extra kernel entries naive versions pay.

Defines blowup and allocator-induced false sharing, which per-processor heaps under a bounded global heap avoid.

The design statement for per-CPU caches built on restartable sequences and a hugepage-aware back end for TLB reach.

States linearizability and the consensus hierarchy and builds both into working stacks, queues, lists and hash tables.

The lock-free queue later libraries copy, with the counted pointer against ABA and a two-lock queue beside it.

The standard-track form of safe reclamation, fixing when a retired node may be freed while a reader still holds it.

The kernel's own statement of RCU as publish, wait for readers and keep old versions, with a free read side.

Defines liburcu's quiescent-state, signal-based and general RCU flavours and measures each read side against locks.

Defines work and critical path, proves the work-stealing bound, and shows they alone predict a runtime's speedup.

States the work-first principle, that overhead belongs on the rare steal path and not on every spawn.

Gives the work-stealing deque a proven atomics form and derives which fence push, take and steal need on Arm and x86.

Fixes fork-join and tasking semantics, and the wait and binding controls deciding if idle workers spin, sleep or move.

The shipping work-stealing runtime, arenas and task groups over a deque, the home of grain size and spin-before-sleep.

The one account tying first touch, policy scope, zone reclaim and page movement together from the implementer's side.

Defines nodes, zonelists and the distance-ordered fallback that places an allocation once local memory runs out.

The normative statement of policy scopes, every mode including weighted interleave, and the cpuset intersection rule.

Defines numa_hit, numa_miss and numa_foreign, the counters that show whether a policy put pages where it said.

Reference implementation of the policy API, prints the distance table and binds a binary that cannot be rebuilt.

Explains the firmware-rated latency and bandwidth per initiator and target, and memory-side caches, that rank nodes.

Where Intel names the mesh, UPI socket links, the directory-running home agent, and how SNC splits the cache.

Defines SNC on current parts as one node per compute die, and fixes the numactl and numastat checks of placement.

Discloses the I/O die, GMI and xGMI links, the NPS modes with their interleave widths, and the cache-as-NUMA override.

Defines the mesh, the home nodes holding the system cache and snoop filter, and the gateways joining sockets or CXL.

Defines per-page migration of a running process, and a query reporting each page's node, the direct test of first touch.

Defines the hinting-fault sampling behind automatic balancing and tiering, and warns the overhead may not pay off.

Proves against the kernel balancer that controller and link congestion, not remote latency, is what placement manages.

Measures the node-to-node latency and bandwidth matrix and loaded latency on the x86 at hand, which no datasheet states.

Tabulates measured bandwidth by NPS mode, cores per die, boost and SMT, so the NPS trade-off is shown, not asserted.

Defines the calls the kernel answers without a mode switch, and the clocksource condition for skipping the trap.

Separates a syscall's trap cost from its cache and TLB pollution, and shows the pollution can dominate.

Measures syscall and context switch cost across kernel releases and traces each slowdown to a named mitigation.

States the goals aio failed, and which io_uring features remove a syscall and which remove a copy.

Measures io_uring's polling modes against libaio and SPDK, and shows the kernel poller needs its own core.

Defines lag and virtual deadline, which the default class schedules by, and the slice request in sched_setattr.

Proves cores sit idle while runnable threads queue, and gives the invariant checker that found the load-balancer bugs.

Defines cpu.max throttling, cpu.weight and the cpusets that bound affinity, the controls behind every container limit.

Defines the governors, driver and boost switch that set a core's frequency, the sysfs state a measurement records.

Ties isolcpus, nohz_full, IRQ affinity, RCU offload and cpusets into one recipe, and lists the jitter it leaves.

Defines the polling, software coalescing, busy polling and IRQ suspension knobs that trade interrupts against latency.

Defines the full bypass model, pinned poll-mode cores with no interrupts, that every kernel path is measured against.

Measures an in-kernel programmable path against DPDK and the stack per core, with the full configuration published.

Separates direct and indirect NIC interrupt cost, measures the stack against bypass, and is where IRQ suspension began.

Defines the socket and UMEM rings handing XDP frames to user space, and the zero-copy and need-wakeup modes.

Defines classes of service, cache masks, bandwidth allocation and monitoring IDs, the model resctrl exposes.

Defines the filesystem through which Linux exposes Intel, AMD and Arm partitioning, and the schemata format.

Maps Arm's cache portion and bandwidth controls onto resctrl's schemata, and states which platform limits apply.

Shows at fleet scale that cycles per instruction alone finds an interfering neighbour and the one to throttle.

Shows cache ways, cores, bandwidth and power must be partitioned together, or batch work reaches the tail.

Shows why fan-out makes a rare slow server a common slow request, and names the techniques that tolerate variance.

Defines the stall band that out-of-order hardware cannot hide and a context switch cannot amortise.

Shows that a summary without a max discards the samples that define the tail, and closed-loop load never records them.

The original definition of the recording error, with arithmetic for how far a reported percentile sits from the truth.

Keeps the whole distribution at fixed relative precision in constant time, so the far percentiles and max survive.

The reference wakeup-latency measurement for Linux, whose README states that an unloaded run proves nothing.

Counts the noise a spinning thread suffers and attributes each event to NMI, IRQ, softirq, thread or hardware.

Derives the queueing-ideal tail and attributes the excess to scheduling, interrupt placement, power saving and NUMA.

Measures with code the page-fault, TLB-shootdown and writeback stalls that memory mapping hides from the caller.

Defines the host-side polling after a vCPU halt that trades idle host CPU for guest wakeup time, unseen by the guest.

Shows that open and closed load models disagree on response time and scheduling gains, with rules for choosing one.

Issues requests on a fixed schedule and times each from when it was due, so server stalls reach the percentiles.

Shows the tail, not throughput, caps a latency-critical server's utilisation, and how far co-located work lowers it.

Pairs latency-critical services with an open-loop harness that records sojourn against service time per request.

Measures the key, value and inter-arrival distributions of live key-value traffic, the shape load generators imitate.

Measures with code the floor for handing a cache line between cores, which every queue and lock is built on.

States the design rule that removes write contention outright, using a contended increment's cost as the argument.

Adds cached indices to a single-producer single-consumer ring and shows with counters the coherence traffic removed.

Applies the single writer rule and cache-line padding to a ring buffer, with the queue comparison that motivated it.

Carries the single writer and batching rules through a whole transport, the reference beyond one in-process queue.

Derives the cache blocking every fast CPU GEMM still uses by refining a memory model until the packed kernel falls out.

Reduces a BLAS to one register-tile micro-kernel per architecture and states which loop owns which level of cache.

Builds a register-tile kernel step by step and shows where outer-loop unrolling wins and where a vendor BLAS still does.

Sets run-time dispatch for a BLAS, one kernel table per microarchitecture chosen as a DYNAMIC_ARCH build loads.

Fixes the data-type table, packed weight format and fused post-ops a CPU GEMM must expose to an inference graph.

Fixes the fused attention pattern, f32 accumulation under bf16 inputs and the shapes the fast CPU path accepts.

Generates VNNI and AMX kernels at run time under PyTorch, TensorFlow and OpenVINO, and calls Compute Library on Arm.

Defines the quantized block formats and the per-ISA dot-product kernels over them that every llama.cpp type rests on.

Where new quantization types, kernels and thread pools land first, each with the perplexity and speed table behind it.

Holds the CPU provider's GEMM, int8 and int4 MatMul kernels, dispatched per ISA at run time from SSE to AMX and SME.

States precision defaults per ISA, the int8 path through oneDNN and the streams model that turns cores into throughput.

Defines the affine scale and zero-point scheme with integer accumulation that every int8 CPU runtime still implements.

States where int8 saturates on pre-VNNI x86, the compensation that makes signed by signed work, and what VNNI removes.

Defines the QDQ form against QOperator and dynamic against static, and which sign choices are safe on which CPUs.

Where new quantization types, kernels and thread pools land first, each with the perplexity and speed table behind it.

Replaces unpacking and multiplying low-bit weights with bit-sliced lookups, so a narrower weight costs less to apply.

Defines the architectural counters, what a PEBS sample captures, and why rdtsc counts time, not cycles, under DVFS.

Defines the arch_prctl permission Linux requires for AMX tile data and the trap a tile instruction takes until granted.

Where new quantization types, kernels and thread pools land first, each with the perplexity and speed table behind it.

The normative definition of NEON, SVE and SVE2 instructions and of the scalable vector and predicate register model.

Walks through SME2 int8 and f32 matmul and gemv kernels and a lookup-table path, on a unit so far only in client parts.

Sets the physical-core default, the affinity it implies and the spin-wait controls that trade idle CPU for latency.

States the vendor defaults, one thread per core, SMT siblings off, core type by precision and one socket for latency.

Where new quantization types, kernels and thread pools land first, each with the perplexity and speed table behind it.

Defines the quantized block formats and the per-ISA dot-product kernels over them that every llama.cpp type rests on.

Holds the memory clock sweep with all else fixed, the token rate following it and flattening after a few threads.

Measures decode kernels on a Xeon as DRAM-bound, so AMX pays at batch one only once bytes per token shrink, with code.

Holds CPU-only entries whose logs show the batched Offline case lost to GPU entries at the same accuracy floor.

Where Intel states what Sapphire Rapids added: larger L2 and L3, DDR5, CXL, AMX and on-die accelerators.

Measures L3 and memory latency across the tiled mesh and the slow clock ramp the vendor overview omits.

The designers' statement of what changed: fewer, larger dies, a bigger shared L3, faster DDR5 and socket links.

Measures per-die L3 under sub-NUMA clustering and the die-crossing cost on Granite Rapids beside Turin.

Bandwidth-bound codes on Sapphire, Emerald and Granite Rapids and Sierra Forest with clocks, SMT and compiler stated.

The designers' account of the Zen 4 core and how it yields Genoa, Genoa-X, Bergamo and Siena.

Tests the same-core claim for Zen 4c: cache latency, clock ceiling and core-to-core paths beside clock-matched Zen 4.

Where AMD states when the op cache feeds micro-ops, and the fusion and alignment rules for hot loops.

Defines Turin: Zen 5 or Zen 5c dies, which parts double die-to-IO links, NUMA modes and full-width AVX-512.

Measures what wider die-to-IO links and faster DDR5 do for Turin bandwidth, and where latency rose over Genoa.

Where AWS states which Neoverse core, ISA revision, mesh, caches and compiler flag each Graviton generation carries.

States every stage of one Arm core from fetch to issue, then per-instruction latency, throughput and pipe assignment.

States the coherency fabric, LPDDR5X fit and MPAM cache and memory partitioning on Grace.

States the timings and fusion rules of the narrower N line core in Cobalt 100 and Yitian.

Where Ampere states the N1 part: private L2 per core, shared system cache, mesh and DDR4 fit.

Measures Neoverse V2, Golden Cove and Zen 4 in-core at fixed clock, and each socket's clock under vector load.

One SVE workload run on Graviton 3, Graviton 4, Yitian and Axion with compiler, runs and spread stated.

Measures a sustained rename width below the stated one, cache latencies, mesh behaviour and cross-socket cost on V2.

Measures structure sizes, cache latencies and mesh behaviour of N2 on Yitian, the core Cobalt 100 carries.

Puts vendor slides beside measurements of the predictor, small instruction cache, private L2 and long memory latency.

Defines base against peak, rate against speed, the threading models a speed run may use and an Arm reference machine.

Where the committee states how workloads were chosen and hardened, and defines the rolling round-robin rate.

Measures with counters what each workload stresses on x86 and Arm server parts, beside data-centre and inference suites.

Fixes model, accuracy floor and query pattern per scenario, so a Server score is throughput under a latency bound.

Shows standard suites misproject data-centre servers, and states the fleet-matching method the suite is built by.

Defines sustainable bandwidth as what unit-stride loops get, not bus peak, and machine balance as flops per access.

Sets the array size rule, timing over repeated trials, and counting bytes a loop asks for, not what the cache moved.

Origin of the one-mechanism-per-test method for memory, system call, pipe and socket latency, and what each leaves out.

Isolates memory-level parallelism from load latency as separate tests, with DVFS held off before timing, x86 Linux only.

Shows why kernel mode with interrupts off matters, removes harness overhead, then recovers cache replacement policies.

Origin of the rule that normalised results take the geometric mean, which a SPEC ratio and the crimes list rest on.

Checklist of evaluation faults from sub-setting and improper baselines to arithmetic means of ratios, each with a fix.

Sets which mean fits costs, rates and ratios, when confidence intervals are owed, and the absolute base a speedup needs.

Decides how many builds, runs and iterations an experiment needs by measuring at which level the variation arises.

Fleet counter profile showing services stall on instruction fetch and burn cycles in shared routines, which SPEC lacks.

Folds the AVX-512 subsets into one versioned level and adds BF16 and FP8 forms, pending a shipped part and a run.

Ties APX, with doubled x86 registers, AVX10.2 and AMX FP8 tiles to Diamond Rapids, pending silicon and a public run.

The ratified vector ISA, shipped only as IP and chiplets, pending a socketed server part and a run against Arm or x86.

The Zen 6 server family, so far a press release with no shipped part, pending shipment and a public run against Zen 5.

The E-core-only sockets after Sierra Forest, shipped with vendor multiples footnoted off the page, pending a public run.

Custom Arm cores with statically partitioned SMT and no architecture document, pending a specification and a public run.

Vendor timing tables for the core shipped in Graviton 5 and previewed in Cobalt 200, pending a public run on the core.

Defines memory pooled across hosts on a coherent link, with latency so far estimated, pending a run on a shipped pool.

Measures expansion devices with frequency and SMT fixed, the nearest run to every field, pending compiler and flags.

Defines the data buffer behind MRDIMMs, whose vendor bandwidth claims name no method, pending a run against RDIMMs.

Lets a BPF program schedule at run time with safe fallback, once a run against the default scheduler states every field.

Lands payloads straight in user memory on header-splitting NICs, pending the implementer's epoll run naming every field.

Table-lookup kernels for low-bit weights, with a baseline stated but no frequency, compiler or flags, pending those.

Generated small sorts shipped in libc++, timed by CPU family with no model, compiler or flags stated, pending those.